一种FPGA配置文件压缩算法  

FPGA Configuration Compression Algorithm

作　　者：邢虹[1] 童家榕[1] 王伶俐[1] 

机构地区：[1]复旦大学专用集成电路国家重点实验室,上海201203

出　　处：《计算机工程》2008年第11期260-262,共3页Computer Engineering

基　　金：国家自然科学基金资助项目(60676020)

摘　　要：基于现场可编程门阵列(FPGA)的可重构系统具有高性能和高灵活性,但随着FPGA规模的不断扩大,配置文件规模相应增加,导致可重构计算时间过长。该文提出一种FPGA配置文件压缩算法VLZW,降低了对片外存储器的容量要求,通过减少每次重构传送的配置数据缩短了系统重构时间。The reconfigurable system based on Field Programmable Gate Array（FPGA） has high performance and flexibility. With the enlarging of FPGAsize, the dramatic increase in configuration data size has resulted in a corresponding increase in the time required for reconfiguration. This paper proposes a FPGA configuration compression algorithm VLZW which can reduce the off-chip memory required for storing FPGA configurations. This algorithm cuts down the reconfiguration time of the system by reducing the transmittal configureation data.

关 键 词：现场可编程门阵列 配置文件压缩 可重构 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]