一种动态VLIW调度机制的研究和实现  

Research and Implementation of a Dynamic Scheduling Mechanism for VLIW Processors

作　　者：李云照[1] 王志英[1] 沈立[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2008年第7期90-93,共4页Computer Engineering & Science

基　　金：国家自然科学基金资助项目(90407022)

摘　　要：VLIW结构是开发ILP的一种重要手段,其优点是结构规整简单、硬件复杂度低。但是,完全依靠编译器进行指令调度的机制限制了VLIW结构性能的提高。本文提出了一种基于确定指令延迟的动态VLIW调度机制,该机制利用大部分指令执行时间确定的特点,根据运行时信息重新调度指令的执行顺序,以进一步开发ILP。在FPGA上的实验结果表明,该机制具有线性的硬件复杂度。The VLIW （Very Long Instruction Word） architecture is one of the most important means to explore ILP （Instruction Level Parallelism）. It has the advantages of regular structure and low hardware complexity. But the exploration of ILP is limited by only the compiler＇s instruction scheduling. A dynamic scheduling mechanism for VLIW processors which is based on the deterministic latency of instructions is proposed in this paper. It schedules instructions according to the real-time information, and maintains the data dependency using the deterministic latency scheme. The results of experiments on FPGA indicate that the mechanism features linear hardware complexity.

关 键 词：超长指令字 动态调度 确定延迟 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]