二维离散余弦变换及其逆变换的VLSI实现  

VLSI Design of 2-Dimensional Discrete Cosine Transform and Its Inverse

作　　者：李晗[1] 孙义和[1] 向采兰[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《微电子学》2008年第3期326-329,共4页Microelectronics

摘　　要：针对适用于H.263及H.264视频压缩协议的编解码算法,二维离散余弦变换(DCT),及二维反离散余弦变换(IDCT),设计了ASIC高速电路,并完成了电路的FPGA模拟验证。在高速算法设计方面,利用一维变换来实现二维变换,通过对变换矩阵的特殊处理,使得一维变换中只含移位和加法运算;在电路设计方面,采用流水线结构并行处理数据,用寄存器堆实现矩阵的转置。对算法及电路设计的优化和改进,大大减少了完成一个矩阵二维正反变换所需要的周期数,提高了电路的吞吐率和运算速度。ASIC设计采用0.18μm CMOS工艺,在最坏情况下,综合电路可达到的最高频率为250MHz;FPGA模拟验证最高频率可达170MHz。High-speed ASIC of 2-dimensional discrete cosine transform （DCT） and its inverse （IDCT） was designed for H. 263 and H. 264 video compression applications. The circuit was verified by FPGA software. For highspeed algorithm design, 1D-DCT/IDCT was used to implement 2D-DCT/IDCT. Meanwhile, the transforming matrixes were specially optimized to make 1D operation composed of only additions and shifts; and pipelining was introduced in the circuit design to make data disposed in parallel, and register pile was adopted for matrix transposing. By improving and optimizing the algorithm and circuit design, the number of cycles required for coding and decoding a data matrix using 2D-DCT and 2D-IDCT was reduced. ASIC simulation based on 0. 18 μn CMOS technology showed that the synthesized circuit had a max frequency of 250 MHz in the worst ease and a max frequency of 170 MHz in FPGA verification.

关 键 词：视频压缩 离散余弦变换 反离散余弦变换 ASIC FPGA 

分 类 号：TN432[电子电信—微电子学与固体电子学]