具有蝶型单元的FFT在FPGA上的实现  

Implementation of High Speed FFT with Butterfly Unit on FPGA

作　　者：淮永进[1] 屈晓声[2] 

机构地区：[1]中国科学院微电子研究所,北京100029 [2]北京航空航天大学电子信息工程学院,北京100083

出　　处：《微电子学》2008年第3期342-344,348,共4页Microelectronics

基　　金：国家自然科学基金资助项目(40571097)

摘　　要：描述了一种使用FPGA实现FFT处理器的方法,基于按时间抽取(DIT)基-4算法,采用4组RAM并行为蝶型单元提供数据,使用交换器对数据进行重行排序。实验结果表明,该方案保证了运算正确性、运算精度和实现复杂度。提出了两种改进的设计思路及方法,使处理器可以获得更高的处理速度。Design and implementation of FFT with FleA based on decimate in time （DIT） Radix-4 algorithm was discussed, in which 4 RAM blocks were used to supply data for butterfly unit and switches were used to re-order data. Experimental results showed that, under prerequisite of accuracy and complexity, this method improves the operating clock and processing rate. Two ways to improve FFT processor for higher processing rate were also proposed.

关 键 词：快速傅里叶变换 蝶型单元 基-4算法 FPGA 

分 类 号：TN919[电子电信—通信与信息系统]