具有邻域子空间的电路模块的高效测试生成  

Efficient Test Generation for Circuit Module with Contiguous Subspace

作　　者：肖继学[1] 陈光 谢永乐[1] 

机构地区：[1]电子科技大学自动化学院

出　　处：《微电子学》2008年第3期358-362,368,共6页Microelectronics

基　　金：国家自然科学基金资助项目(90407007)

摘　　要：对于VLSI中具有邻域子空间的电路模块,提出了一种高效测试生成方法。利用该方法得到了行波进位、超前进位加法器的测试生成,并予以了硬件实现。8位、16位和32位两种加法器的测试实验表明,这些测试生成能够使单固定型故障的故障覆盖率达到100%,双故障覆盖率分别达到99.996%以上以及100%,故障定位率得到了显著提高。测试矢量的数目仅与邻域子空间的大小有关。由于原电路中加法器的复用,两种加法器测试生成的硬件实现仅需额外的一个逻辑与门,将硬件开销降至最小。An efficient test generation approach was proposed for circuit module with contiguous suhspace in VLSI, which was applied to ripple carry adder and carry look-ahead adder. Test generators were obtained and implemented in hardware. Based on the generation, test experimentations for 8-hit, 16-hit and 32-bit ripple carry adder and carry look-ahead adder were performed. Results showed that, with this test generation, fault coverage up to 100% for single stuck-at fault and more than 99. 996% and 100% for double stuck-at faults could be achieved, respectively, for the two adders tested, and the fault location ratio was improved observably. The test pattern number was only dependent on the contiguous suhspace size. Due to the reuse of adders in the original circuit, only a logic AND gate was needed to implement the test generator for ripple carry adder or carry look-ahead adder, minimizing additional hardware overhead.

关 键 词：加法器 故障 测试生成 集成电路测试 

分 类 号：TN407[电子电信—微电子学与固体电子学] TN7