面积优化的调相DDS软核编译器设计与实现  

Design of Area Efficient Phase Modulation DDS IP Compiler

作　　者：杜伟韬[1] 卢起斌[1] 徐伟掌[1] 杨占昕[1] 

机构地区：[1]中国传媒大学广播电视数字化工程中心,北京100024

出　　处：《微电子学》2008年第3期381-384,共4页Microelectronics

基　　金：国家高技术研究发展(863)计划基金资助项目(2002AA11901015)

摘　　要：为解决设计灵活性和重用问题,取得设计资源和性能的良好平衡,基于泰勒线性插值的ROM压缩方法,设计并实现了一种自动生成带有相位调制功能DDS软核的IP编译器。对关键算法和硬件架构以及代码自动生成原理进行了描述,并且给出了实验结果。To achieve the flexibility and reusability of design, and taking tradeoff between performance and circuit area into consideration, an IP compiler for phase modulation supported DDS core was designed and implemented based on Taylor interpolation ROM compress technique. The principle of HDL code auto generation was dealt with. The key algorithm and hardware architecture were described in detail. And finally, experimental results were discussed.

关 键 词：直接数字频率合成 泰勒插值 IP编译器 FPGA 

分 类 号：TN492[电子电信—微电子学与固体电子学]