一种双采样保持器6位20 MSPSA／D转换器  

A 6-Bit 20 MSPS A/D Converter Using Double SHA

作　　者：洪岳炜[1] 王百鸣[2] 陈静秋[3] 

机构地区：[1]深圳大学光电子学研究所,广东深圳518060 [2]深圳大学信息工程学院EDA技术中心,广东深圳518060 [3]深圳大学物理科学学院,广东深圳518060

出　　处：《微电子学》2008年第3期397-400,共4页Microelectronics

基　　金：国家自然科学基金重大研究计划资助项目(90407001);深圳市科技计划资助项目(200512)

摘　　要：提出了一种双采样保持器的6位20 MSPS A/D转换器。电路采用两个彼此串联的采样保持器和一个3位并行式A/D转换器。伴随着20MHz双相差分时钟,3位并行式A/D转换器在时钟前半周期转换出高3位数字,并产生3阶模拟余量;在时钟后半周期,再利用该余量转换出低3位数字。既充分利用时钟时间,又充分提高了器件的利用率,大大降低了器件成本。通过实验仿真,进行了相关测试分析,给出了动态测试结果。A new 6-bit 20 MSPS A/D converter using double sample/hold amplifiers （SHA） was designed. The ADC circuit consisted of two SHA＇s, which were connected in series, and a 3-bit parallel ADC. With a 20 MHz-differential-clock, the 3-bit ADC converted the upper 3 bits and generates the 3rd-order remainder of analogue quantity in the first half of clock cycle, and converted the lower 3 bits using the 3rd-order remainder of analogue quantity at the second half of clock cycle. The new design can make full use of both the clock time and device efficiency, and the number of electronic components can be greatly reduced. Experiment was made to test the dynamic performance of the device

关 键 词：A/D转换器 有效位数 模拟余量 

分 类 号：TN792[电子电信—电路与系统]