高速并行Turbo译码中的交织器技术研究  

Research on Hign Throughput Parallel Interleaver Based on Collision-free

作　　者：黄卉[1] 王辉[1] 

机构地区：[1]南京工业大学信息科学与工程学院,江苏南京210009

出　　处：《通信技术》2008年第6期83-85,共3页Communications Technology

摘　　要：为了适应高速率通信系统的发展要求,Turbo码可采用并行译码的结构方式来降低时延。然而在并行Turbo码译码中,交织器的随机特性可能会导致多个数据同时写入同一个存储器,这就造成了存储器的访问冲突。如何设计出无冲突交织器是并行Turbo译码器的设计难点。文中对当前国内外的并行Turbo译码无冲突交织器设计方案进行了综述,对几种新的交织器分析研究。For high data rate applications, the parallel decoding scheme can reduce the decoding delay greatly. However, in the parallel decoding scheme, the random characteristics of interleaver may probably induce data collision due to that the multi-data are written into the same RAM at the same time. The challenge in the design of Turbo parallel decoding is how to design the collision-free interleaver. This paper gives an overview on the research of Turbo parallel collision-free interleaver at home and abroad in recent years.

关 键 词：并行译码 数据冲突 并行交织 

分 类 号：TN911.22[电子电信—通信与信息系统]