A Robust Novel Technique for SPICE Simulation of ESD Snap-back Characteristics  

作　　者：JIAO Chao YU Zhiping 

机构地区：[1]Institute of Microelectronics, Tsinghua University, Beijing 100084, China

出　　处：《Chinese Journal of Electronics》2008年第1期71-74,共4页电子学报（英文版）

基　　金：This work is supported by the National Natural Science Foundation of China （No. 90307016）.

摘　　要：This paper presents a robust and novel technique for the circuit simulation of ESD （ElectroStatic discharge） snap-back characteristics. A new linearization scheme by introducing current as independent variable for the avalanche current model in ESD evaluation shows a good convergence behavior during ESD stress simulation. This technique is compatible with the traditional circuit simulator based on the Modified nodal analysis （MNA） like SPICE. We have implemented the well known Amerasekera＇s ESD MOSFET model in SPICE3fS. The commonly used ESD protection configurations such as GGNMOS （Gate-grounded NMOS） and GCNMOS （Gatecoupled NMOS） are simulated and the simulation results demonstrated the good convergence behavior of this new technique.

关 键 词：ElectoStatic discharge （ESD） SPICE（Simulation program with integrated circuit emphasis）simulation Snap-back Gate-grounded NMOS （GGN-MOS） Gate-coupled NMOS （GCNMOS） Compact model. 

分 类 号：TN492[电子电信—微电子学与固体电子学]