基于改进混合式CORDIC算法的直接数字频率合成器设计  

Design of Direct Digital Frequency Synthesizer Based on Improved Hybrid CORDIC Algorithm

作　　者：张晓彤[1] 辛茹[1] 王沁[1] 李涵[1] 

机构地区：[1]北京科技大学计算机系,北京100083

出　　处：《电子学报》2008年第6期1144-1148,共5页Acta Electronica Sinica

基　　金：北京市科技计划重大项目"交互式有线数字电视信道传输核心技术开发"(京科技发No.[2002]188);北京市科技计划"SOC设计服务及重点产品关键技术研究"(No.D0306008041021)

摘　　要：提出一种新的面积优化的直接数字频率合成器设计方案.采用改进混合式CORDIC算法,通过削减旋转相位判断电路和乘法单元,改进和调整相位旋转误差,并利用简单的移位和加/减电路完成复杂的幅度修正,降低了电路复杂度,缩减了电路规模.结构上采用流水线式多级循环迭代技术,实现移位和加/减电路的高度复用.实验结果表明本方法输出频谱杂散小于-70dB,并在运算速度和资源利用率上具有一定的优势.该设计已成功用于宽带网络SoC芯片的频率调制模块.An area-efficient design proposal of a direct digital frequency synthesizer is presented. It adopts the improved hybrid coordinate rotation digital computer （CORDIC） algorithm. By cutting down all of rotational phase decision circuits and multipliers, adjusting rotational phase error, and finishing complicated amplitude amendment with simple shift and addition-subtraction circuits, the proposal can decrease the hardware complexity and reduce the circuit area. The pipeline multilevel loop iteration implementation architecture is adopted for reusing shifting and addition-subtraction components highly. The simulation indicates that the miscellaneous interference of output frequency spectrum is lower than - 70dB.And the design has superior speed and resource usage. The VLSI design proposal has been used in a frequency modulation module of the broadband network System on Chip （SoC） platform.

关 键 词：直接数字频率合成器 混合式CORDIC 面积优化 多级循环迭代 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]