低功耗互补传输门绝热逻辑和时序电路的设计  

Low-power Complementary Pass-transistor Adiabatic Logic and Sequential Circuits

作　　者：邬杨波[1] 李宏[1] 胡建平[1] 

机构地区：[1]宁波大学信息科学与工程学院,浙江宁波315211

出　　处：《宁波大学学报（理工版）》2008年第2期195-200,共6页Journal of Ningbo University：Natural Science and Engineering Edition

基　　金：浙江省自然科学基金(Y104327);浙江省教育厅项目(20070981)

摘　　要：研究了采用二相非交叠功率时钟的绝热触发器及时序电路的设计,介绍了采用二相无交叠功率时钟的互补传输门绝热逻辑(CPAL)电路,并分析了其工作原理.该电路利用nMOS管自举原理对负载进行全绝热驱动,从而减小了电路整体功耗,且CPAL能耗几乎与工作频率无关.提出了性能良好的低功耗绝热D、T和JK触发器,并与其他几种绝热触发器进行功耗比较,给出了绝热时序电路的一般设计方法,并作为实例采用应用绝热D触发器设计了十进制计数器.SPICE程序模拟表明:设计的电路具有正确的逻辑功能及低功耗的优点.We present a complementary pass-transistor adiabatic logic （CPAL） for low-power design, which is driven by two-phase AC power supply. The bootstrapped nMOS switch is employed to eliminate non-adiabatic loss on output loads. Its energy dissipation is in less dependency on power-clock frequency. The adiabatic D, T and JK flip-flops are proposed. A synthesis method for adiabatic synchronous sequential circuits is proposed. A practical sequential system based on the proposed adiabatic D flip-flop is verified. SPICE simulations demonstrate that the designed circuits have correct logic function and considerable power saving.

关 键 词：低功耗技术 能量恢复 绝热触发器 时序逻辑 CPL电路 

分 类 号：TP331.2[自动化与计算机技术—计算机系统结构]