高性能通用H.264/AVC变换编码的硬件结构设计  

High performance multi-transform coding hardware architecture design for H.264/AVC

作　　者：石冰[1] 郑伟[1] 李东晓[1] 张明[1] 

机构地区：[1]浙江大学信息与电子工程学系,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2008年第6期933-938,共6页Journal of Zhejiang University：Engineering Science

基　　金：国家自然科学基金资助项目(90307002)

摘　　要：为了在硬件设计时保证实时编解码的前提下尽量提高硬件使用率,减少芯片面积,提出了一种可以处理H.264/AVC中所有变换的通用变换编码结构.通过将这几种变换算法化简,并且研究它们之间的相似性,本设计将处理单个变换的结构合并成一个通用变换编码结构.仿真和综合后的结果表明,与其他设计相比,该结构有更小的硬件复杂度,并且在50 MHz的频率下就可以达到实时编解码HD 1080i(1920×1088@60fps)格式的H.264/AVC码流的要求,有助于降低功耗.同时,从而灵活地调整该结构以达到不同的数据处理速率,从而满足各种数据处理速率的H.264/AVC编解码系统.In hardware architecture design, in order to increase the hardware utilization and minimize the hardware cost, and maintain the real-time coding at the same time, a multiple transform coding architec ture which could process all the transforms in H. 264/AVC was proposed. By simplifying these transforms and exploring their similarities, the proposed design merges the architectures processing individual transforms into a multi transform coding architecture. Simulation and synthesis show that compared with other designs, this design has lower hardware cost, and can meet the requirement of real-time coding/decoding HD 1080i （1 920×1 088@60 fps） video at 50 MHz, which helps to reduce the power consumption. This architecture can be easily adjusted to achieve different data processing rates, so that it can be embedded into H. 264/AVC coding systems of various data processing rates.

关 键 词：整数变换 HADAMARD变换 H.264/AVC 硬件结构设计 

分 类 号：TN919.8[电子电信—通信与信息系统]