中子墙探测器前端读出电子学电路设计的改进  

An improved circuit design for front-end read-out electronics of neutron detection wall detectors

作　　者：吴鸣[1] 苏弘[1] 彭宇[1] 李小刚[1] 马晓利[1] 千奕[1] 刘义才[1] 

机构地区：[1]中国科学院近代物理研究所

出　　处：《核技术》2008年第6期476-480,共5页Nuclear Techniques

基　　金：国家自然科学基金项目(10675153)资助

摘　　要：本文介绍了一种基于复杂可编程逻辑器件设计的大规模探测器前端电子学系统电路,提出了一种优化的电路设计,它的主要功能是对中国科学院近代物理研究所在建的中子墙探测器的输出信号进行处理,实现了多路的信号甄别,能量-幅度装换(QAC),时间-幅度转换(TAC),多道信号输出等功能。突出特点:采用新型DMOS开关,测量精度高、功耗低、速度快、元件少等。在大型探测器阵列前端电子学系统中有着广泛的应用前景。The circuit for front-end electronics for neutron detection wall based on CPLD, which can deal with the output signal of the neutron detection wall in IMP, is introduced in this paper. An improved circuit design is proposed for front-end read-out electronics of neutron detection wall detector. The system consists of coincidence unit, QAC unit, TAC unit, and multiplexer unit etc. We use CPLD to construct the main circuit in the design. Compared with the circuits constructed by separate devices, the new circuit has features such as the DMOS switch used, higher precision, less components, lower cost and lower dissipation. The circuit we developed can be widely used in nuclear measurement system of physics experiment with large-scale detector array to form front-end read-out electronics of data acquisition system.

关 键 词：探测器 CPLD 能量-幅度装换(QAC) 时间-幅度转换(TAC) DMOS 

分 类 号：TN78[电子电信—电路与系统]