基于FPGA的系数可调FIR滤波器设计  

Design of FIR Filter with Adjustable Coefficients Based on FPGA

作　　者：陈虹[1] 崔葛瑾[1] 

机构地区：[1]东华大学信息科学与技术学院,上海200051

出　　处：《实验室研究与探索》2008年第6期47-50,80,共5页Research and Exploration In Laboratory

摘　　要：根据不同的数字信号处理要求,提出了两种滤波系数在线实时调整FIR滤波器的设计方案:自适应调整和直接设定调整。滤波系数自适应调整利用控制算法对滤波器的实际输出信号和期望信号的差值进行反馈调节,更新滤波系数h。滤波系数直接设定调整利用FPGA中的存储资源存放已知的有限种滤波参数h,构成系数查找表模块。通过数字设定改变查找表地址,修改滤波系数以适应不同的滤波要求。文中以四阶滤波器为例给出了电路模型,并在Matlab环境中对4种滤波特性的系数直接设定调整方案进行了仿真,仿真结果表明滤波特性基本满足设计要求。最后应用A ltera数字信号处理设计平台DSP Builder给出了以FPGA为载体的滤波系数可调整FIR滤波器实现方案。According to the different digital signal processing request, two kinds of design projects of FIR filter with online adjustable coefficients were put forward： adaptive coefficients adjustment and direct coefficients adjustment. Adaptive coefficients adjustment uses adaptive arithmetic to adjust coefficients in feedback structure which is used to regulate the error of actual output signal and expect signal. Direct coefficients adjustment uses memory resources in the FPGA to store coefficients, and then constitutes coefficients look-up table models. The address of look-up table is changed to adapt the different filter requests. In this paper, a four-order filter model with four filter properties was designed, and direct coefficients adjustment was simulated in Matlab. The results of simulation show that its filter properties basically satisfy design requests. Finally, the digital signal processing development environment -- DSP Builder was used to implement this FIR filter with adjustable coefficients on FPGA.

关 键 词：FIR FPGA DSP BUILDER 系数调整器 查找表 

分 类 号：TP319[自动化与计算机技术—计算机软件与理论]