锁相环型频率综合器中的高速分频器  

Researches on the high-speed divider in the PLL frequency synthesizer

作　　者：袁泉[1] 杨海钢[1] 董方源[1] 尹韬[1] 

机构地区：[1]中国科学院电子学研究所

出　　处：《中国科学院研究生院学报》2008年第4期549-553,共5页Journal of the Graduate School of the Chinese Academy of Sciences

摘　　要：对锁相环型频率综合器中的高速分频器进行了较为深入的分析.比较了同步分频器和异步分频器,表明了异步分频器在高频应用中的特点.对相位切换型异步分频器中第1级和第2级2分频电路的实现方案进行了仔细分析和对比,并针对Wang提出的2分频电路中存在的电荷分享问题提出了改进方案,仿真显示改进后的电路有效解决了电路中的电荷分享问题.采用Chartered0.35μm2P4MCMOS工艺,对第1级与改进后的第2级2分频电路整体仿真显示,电路的最高工作频率为3.3GHz,电流消耗为1.9mA.In this paper, characteristics of circuits the design of the high-speed divider in the PLL frequency synthesizer is investigated. The conceming speed and power are compared between the synchronous divider and the asynchronous divider. Considering the different demands for the divide-by-2 circuits in the phase-switching asynchronous divider, several different circuits topology of the divide-by-2 circuits are presented. And the charge sharing problem of the divide-by-2 circuit in a reference paper is solved in this paper. According to the simulation results, the highest working frequency of the first and the improved second divider-by-2 circuits is 3.3GHz, and the current consumption is 1.9mA.

关 键 词：锁相环 异步分频器 同步分频器 电荷分享 

分 类 号：TN433[电子电信—微电子学与固体电子学]