H.264中高吞吐量算术编码器的FPGA实现  

A Hardware Implementation of High-Throughput Arithmetic Coder in H.264

作　　者：王琨[1] 陈新[1] 

机构地区：[1]福州大学物理与信息工程学院,350002

出　　处：《微计算机信息》2008年第17期216-218,共3页Control & Automation

基　　金：福建省科技厅集成电路(IC)技术平台建设(2003Q013)

摘　　要：H.264是国际上最新、最有前途的视频压缩标准,基于上下文的二进制算术编码器(CABAC)是H.264中一种高效的熵编码器,但其算法比较复杂,吞吐量不高。为此,提出了一种高吞吐量算术编码器的电路结构。在递归过程中,通过对两个符号的同时处理而提高吞吐量,从而提高编码速度。整体的电路采用流水线结构,该结构在spartan3FPGA上实现,编码速度达到2bits/cycle,最高的时钟频率可达67.5MHz。H.264 is the newest and the most promising video compressing standard in the world. The context-based adaptive binary arithmetic coding algorithm, which is based on H.264, is an efficient but complicated and low-throughput algorithm. So a high- throughput architecture is proposed. The throughput is improved by processing two symbols every circle in the recursive process, consequently the coding speed is improved. A pipe-line architecture is applied in the whole circuit, which is implemented in the spartan3 FPGA. The coding speed can reach 2bits/cycle and the maximal clock frequency can reach 67.5MHz.

关 键 词：H.264 算术编码 FPGA 流水线 

分 类 号：TN919.81[电子电信—通信与信息系统]