基于FPGA的改进型分组交织器的设计与实现  

Design and Realization of an Improved Block Interleaver Based on FPGA

作　　者：高晶[1] 达新宇[1] 禇振勇 

机构地区：[1]空军工程大学电讯工程学院,西安710077

出　　处：《微计算机信息》2008年第17期228-230,共3页Control & Automation

基　　金：陕西省自然科学基金资助(2006F22)

摘　　要：本文分析了交织器在Turbo码中的重要作用,以及分组交织器存在的缺陷,提出了一种改进型分组交织器的设计与实现方法。该交织器具有算法简单、易于实现、可适应不同数据帧长度传输要求的优点。设计采用Altera公司生产的Cyclone系列器件,利用其片内RAM实现,并基于QuartusⅡ软件平台进行了仿真验证。This article described the role of interleaver in Turbo codes, analyzed the drawback of block interleaver, an improved block interleaver was presented.The interleaver was considered a technique with good virtues such as algorithm simple, easily realized in application and could adapt different data frame.The design used the internal RAM in Cyclone devices of Altera corporation and was verified true by time simulation based on Quartus Ⅱ software platform.

关 键 词：分组交织器 TURBO码 FPGA 

分 类 号：TN911.22[电子电信—通信与信息系统]