高速数据采集系统的新型接口设计  

Design of new type of interface for high-speed data acquisition

作　　者：程霄[1] 刘勇[1] 张龙[1] 李志刚[1] 吴晓松[1] 

机构地区：[1]中国科学院安徽光学精密机械研究所激光中心,合肥230031

出　　处：《电子测量技术》2008年第6期114-116,共3页Electronic Measurement Technology

基　　金：中国科学院安徽光机所激光中心青年基金资助项目(0605)

摘　　要：传统的数据采集系统均以FIFO的存储满或半满标志作为中断请求信号。本设计以CPLD为逻辑控制核心,利用其产生的中断计数模块向DSP发中断请求,有效的解决了存储数据与FIFO容量不匹配的问题,实现了高速数据采集系统的新型接口设计。实验结果表明,该设计不仅有效的提高了数据采集的速度,同时具有接口电路简单、通用性强、易于移植等特点,可广泛应用于通信和图像采集中。Traditional data acquisition system always uses a full flag or half-full flag of FIFO as interrupt request signal sign. This paper introduces the new interface design, which the CPLD works as the logic control core, and uses its interruption module to offer the request signal. Solve the issues that the data being storage not matching with the capability of FIFO. This design not only improves the speed of data acquisition effectively, but also has many advantages, such as with a simple interface circuit, universality, easy to transplant, and other features that can be extensively used in communications and image acquisition.

关 键 词：可编程逻辑器件 先进先出存储器 接口 时序 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]