CIC滤波器的FPGA实现  

Realization of CIC filter based on FPGA

作　　者：范艳根[1] 

机构地区：[1]哈尔滨工业大学微电子中心

出　　处：《黑龙江科技学院学报》2008年第3期206-208,共3页Journal of Heilongjiang Institute of Science and Technology

基　　金：黑龙江省教育厅科学技术研究项目(11511349)

摘　　要：为了解决软件无线电通信系统中频采样之后的极大数据量在基带处理部分对DSP计算的压力,在发射和接收过程中采用采样率变换技术,并引入CIC滤波器实现采样率转换,很好地满足了抗混叠效应的要求。采用常规方法和Hongenauer剪除理论的改进算法完成该滤波器的设计,结果表明:对于5级CIC滤波器,前者最高工作频率为160 MHz,占用228个逻辑单元;后者最高工作频率为193 MHz,占用225个逻辑单元。Quartus II时序仿真验证了两种方法的正确性,而后者更适用于高速多速率信号处理系统。Directed at overcoming the pressure on DSP computation exerted by huge data quantity due to intermediate frequency sampling in the baseband in software radio system, the paper introduces the use of the technique of sample rate conversion in the receiver/sender and cascade integrator comb （CIC） filter to realize digital sampling rate conversion. The method can fulfill the requirement of anti-aliasing effects. This paper is focused on the normal methods and the modified methods to realize 5-stage CIC filter. The result of experiments shows that in the case of 5-stage CIC filter, normal methods operate at the greatest frequency of 160 MHz, using 228 logic elements; the modified methods at the greatest frequency of 193 MHz, using 225 logic elements. Both methods are verified to be valid by timing simulation with Quartus II. The modified methods prove to be more suitable for multi-rate high-speed signal processing system.

关 键 词：软件无线电 采样率变换 CIC滤波器 FPGA 

分 类 号：TN92[电子电信—通信与信息系统]