基于VHDL的正交编码脉冲电路解码计数器设计  

Design of a QEP decode counter based on VHDL

作　　者：胡天亮[1] 李鹏[1] 张承瑞[1] 左毅[2] 

机构地区：[1]山东大学机械工程学院,山东济南250061 [2]山东济南一机床集团有限公司,山东济南250022

出　　处：《山东大学学报（工学版）》2008年第3期10-13,57,共5页Journal of Shandong University（Engineering Science）

基　　金：国家自然科学基金资助项目(50575129)

摘　　要：针对正交编码脉冲电路脉冲(quadrature encoder pulse,QEP)的解码和计数的问题,给出了QEP解码计数器的解决方案.本方案在复杂可编程逻辑器件(complex programmablelogic device,CPLD)中使用VHDL(VHSIChardware descriptionlanguage)实现语言硬件编程.整个解码计数器设计分为脉冲边沿检测器,计数脉冲和计数方向发生器,上下行计数器三部分,成功的解决了由传感器抖动引起频繁换向时准确计数的问题.该解决方案使用Altera公司的Quartus Ⅱ软件进行设计并进行了仿真分析,最后给出了基于此技术的机床数显表的应用实例来说明此技术的可行性和柔性.To solveproblems in decoding and counting of Quardrature Encoder Pulse （QEP）, a design of a QEP decode counter was presented. VHSIC hardware description langurage （VHDL） was used as the programming language, which was implemented in a complex programmable logic device （CPLD）. The whole structure of this design includes three parts ： edge pickers, pulse/direction generator and up/down counter. By using this structure, the counting accuracy in a dithering case was successfully guaranteed. Altera Quartus Ⅱ was used for design as well as simulation analysis. The application in Digital Readout for machine tools was given to improve the feasibility and flexibility.

关 键 词：正交编码脉冲 解码 VHDL硬件语言编程 复杂可编程逻辑器件 

分 类 号：TP273[自动化与计算机技术—检测技术与自动化装置]