DVB-S2系统中LDPC编码的FPGA实现  

FPGA implementation of LDPC encoder in DVB-S2

作　　者：张文俊[1] 王琳[1] 

机构地区：[1]重庆邮电大学编码技术研究所,重庆400065

出　　处：《重庆邮电大学学报（自然科学版）》2008年第4期436-439,共4页Journal of Chongqing University of Posts and Telecommunications(Natural Science Edition)

基　　金：教育部新世纪优秀人才支持计划项目(NCET-04-0601);福建省科技重点项目(2006H0039);重庆市科委自然科学基金项目(CSTC,2007BB2387)

摘　　要：分析了DVB-S2中LDPC码的特点,给出了一种面向FPGA的LDPC码编码实现方案,并采用Verilog HDL语言在Virtex 4 xc4vlx60芯片上实现了该编码器的设计,设计采用多个BlockRAM存储校验位,实现了与同一信息位关联的所有校验位的并行处理,提高了编码速度。综合结果表明:该编码器的吞吐量约为49.95 Mbit/s,在占用资源较少的情况下满足了DVB-S2标准的要求。This paper analyses the characteristics of the LDPC code in DVB-S2, and proposes an encoding architecture for FPGA implemented with Verilog HDL language on the chip of Virtex 4 xc4vlx60. The design method adopts many Block-RAMs to process all the parity bits relating to the same information bit in parallel, thus improving the encoding speed. Synthesis results show that this encoder has a throughput about 49.95 Mbps, which satisfies the demand of DVB-S2 at the cost of low resource occupation.

关 键 词：DVB-S2 低密度奇偶校验码 FPGA 

分 类 号：TN911[电子电信—通信与信息系统]