一种新型NoC拓扑结构的研究  

A new topology for system-on-chip design

作　　者：温东新[1] 朴守业[1] 王玲[1] 杨孝宗[1] 吴智博[1] 

机构地区：[1]哈尔滨工业大学计算机科学与技术学院,哈尔滨150001

出　　处：《高技术通讯》2008年第7期699-702,共4页Chinese High Technology Letters

基　　金：863计划(2006AA01A103);国家自然科学基金(60706004)资助项目

摘　　要：提出一种片上网络(NoC)拓扑结构——Spidernet,并对其网络的主要属性如节点度、网络直径、连通度、平均最短路径和平均最短布线等进行了研究。首先将 Spidernet 与其它拓扑结构的属性进行比较,并采用模拟退火的布局映射算法,根据NoC的布局结构,将不同的节点放入 NoC 网格中,即给出一组被绑定和调度的可供选择 IP 核,在满足 IP 核所占用芯片面积的条件下将选择的 IP 核映射到网络中,目标是最小化平均布线长度。网络拓扑结构图描述文件和 IP 核任务图作为输入。实验中运行基准程序,结果表明提出的网络拓扑结构更适合于将来的 SoC 的片上网络构造。This paper proposes a topology structure for network-on-chip （NoC）, and compares it with other topology networks in terms of five kinds of mainly properties： node degree, network diameter, connectivity, the average shortest circuit path, and the average shortest wire length. A simulated annealing algorithm is applied to embedment of different nodes onto different tiles on a grid NoC platform that act as placeholders in the architecture. Precisely, given an application described by a set of concurrent tasks, already bounded and scheduled onto a list of selected IPs, the problem is to determine how to topologically map the selected IPs onto the network. The objective function is to minimize the average wire length on the grid. Topology description file and IPs tasks graph are regarded as inputs. The experiment results show that this topology has better performance on cost/performance layout by running benchmarks.

关 键 词：SOC NOC 拓扑结构 Spidemet 

分 类 号：TN47[电子电信—微电子学与固体电子学]