多路可变速率同步组合器技术研究  

The Research on Multichannel Rate-variable Synchronous Combiner Technology

作　　者：郑宜忠[1] 

机构地区：[1]中国电子科技集团公司第五十四研究所,河北石家庄050081

出　　处：《无线电工程》2008年第6期11-13,共3页Radio Engineering

摘　　要：基于同步时分复用原理,利用FPGA大规模集成电路技术,实现多种时钟、多种信息、多种帧结构可任意设置的复杂电路设计。采用动态帧结构技术和多时钟管理技术,将多路同步信息进行组合,并且各路信息速率可在设计范围内任意设置。支路信息数量最大可达4路,组合种类可达1000多种,能满足多种应用需求,解决现有部分传输设备和终端设备之间不能互连的问题。Based on synchronous time division multiplexing theory, using FPGA LSI technology, the design of complicated circuit is realized, in which the multiple clocks, multiple kinds of information and multiple frame structures can be set discretionarily. By adopting dynamic frame structure and multi-clock management technologies, multiple channels of synchronous information can be combined and the information rate of each channel can be set discretionarily within the designed range. With the number of branches reaching up to four and the combination modes attaining over one thousand, the combiner can satisfy the demands of multiple applications, and solve the problem that some existing transmission equipment and terminal equipment can not be interconnected.

关 键 词：多路复用 时钟 可变速率 任意组合 

分 类 号：TN79[电子电信—电路与系统]