A Σ-Δ Fractional-N PLL Frequency Synthesizer with AFC for SRD Applications  

一种用于短距离器件的带自校准的Σ-Δ分数分频频率综合器(英文)

作　　者：章华江[1] 胡康敏[1] 洪志良[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《Journal of Semiconductors》2008年第7期1298-1304,共7页半导体学报（英文版）

摘　　要：A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.介绍了一种应用于433/868 MHz频段短距离器件的分数分频频率综合器.采用带自适应频率校准的宽带压控振荡器来覆盖要求的频段,并采用3位量化、3阶的Σ-△调制器来实现分数分频和改善锁相环的带外噪声.测试结果表明,自适应频率校准能够正常工作,压控振荡器的频率调节范围为1.31 -1.18GHz,在3MHz频偏处的带外噪声为-139dBc/Hz,分数毛刺低于-60dBc.芯片采用0.35μm CMOS工艺,芯片面积仅为1.8mm^2,功耗仅为57mW.

关 键 词：short range device phase locked loop adaptive frequency calibration frequency synthesizer SIGMA-DELTA 

分 类 号：TN74[电子电信—电路与系统]