基于低功耗双边沿JK触发器的异步减法计数器和可逆计数器设计  

Design of Asynchronous BACKWARD Counter and REVERSIBLE Counter based on Low Power Double-Edge-Triggered JK Flip-Flops

作　　者：王芳[1] 唐骞 陈偕雄[1] 

机构地区：[1]浙江大学信息学院 [2]杭州市西湖区信访局,杭州310013

出　　处：《科技通报》2008年第4期527-530,共4页Bulletin of Science and Technology

摘　　要：从JK触发器的激励表和状态转换矢量K图出发,导出了基于单边沿JK触发器的同步、异步减法计数器和可逆计数器的设计方法,给出了双边沿JK触发器的完整状态方程,并以此为基础提出了基于双边沿JK触发器的异步减法计数器和可逆计数器的设计方法。Starting from the excitation table and the K-map of state transform vector of JK flip-flops, the paper derives the designed method of synchronous and asynchronous backward counter and reversible counter based on single-edge-triggered JK flip-flops, and gives the complete state equation of the double-edge-triggered JK flip-flops. Based on it, the design methods of asynchronous backward counter and reversible counter using double-edge-triggered JK flip-flop are proposed.

关 键 词：减法计数器 可逆计数器 低功耗 双边沿触发器 逻辑设计 

分 类 号：TN911.23[电子电信—通信与信息系统]