EPP模式下的并口与FPGA的高速数据通信  

High Speed Data Communication between FPGA and Parallel Interface in EPP Mode

作　　者：谢庭军[1] 刘少君[1] 黄道平[1] 

机构地区：[1]华南理工大学自动化科学与工程学院,广东广州510640

出　　处：《控制工程》2008年第4期440-442,469,共4页Control Engineering of China

摘　　要：介绍了通过EPP协议实现FPGA和计算机并口之间双向高速数据通信的方法,并描述了EPP的操作模式和通信原理;讨论了硬件设计结构、有限状态机实现及相应的并口程序设计,实现了计算机和FPGA之间的高速数据传输,占用FPGA和计算机的时间非常少,尤其在速度快、数据量大的情况下,具有更大的优势。该方法具有一定的通用性。The method to realize high speed data communication between FPGA and PC parallel interface via EPP protocol is introduced.And the operational mode and communication principle of EPP are described.The hard ware designing structure,the finite state machine realization and the corresponding parallel program design are discussed.The high speed data transmission between PC and FPGA is realized.With this method,FPGA and PC are occupied less time,particularly under condition of mess data,more advantages are shown.The proposed method has some generality.

关 键 词：EPP FPGA 有限状态机实现 并口程序设计 高速数据传输 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]