B3G系统中MAC和PHY接口设计与实现  

Design and implementation of the interface between MAC and PHY in B3G systems

作　　者：宁元辉[1] 朱光喜[1] 苏钢[1] 谭力[1] 

机构地区：[1]华中科技大学电子与信息工程系,湖北武汉430074

出　　处：《华中科技大学学报（自然科学版）》2008年第7期5-9,共5页Journal of Huazhong University of Science and Technology(Natural Science Edition)

基　　金：北京邮电大学泛网无线通信教育部重点实验室资助项目;国家高技术研究发展计划资助项目(2003AA12331005)

摘　　要：研究了如何实现超三代移动通信时分双工(B3G TDD)系统中媒质接入控制层(MAC)与物理层(PHY)多通道RocketIO Gbit数据接口.基于模块化思想设计出一种按比特映射方式调整MAC发送数据包格式的透明发送机制;利用各通道轮询方法设计了一种多通道联合自适应数据接收机制,它的片内存储器资源占用率仅为传统FPGA设计的25%.基于该接口模式,仅修改FPGA内几个寄存器值即可实现整个系统的升级,而自适应接收机制使得基站和移动台可以使用同一FPGA代码,即实现了设计的通用性.所有寄存器均由协议处理器通过外部设备互联总线配置(PCI),因此FPGA配置文件只需要生成一次,可节省大量用于产生不同配置文件所需的FPGA布局布线的时间.本接口设计方法在未来移动通信系统中具有广泛的应用价值.Design and implementation of interface of multiple RocketIO gigabit channels between medium access control（MAC） and physical layer（PHY） in B3G TDD system were investigated. Based on module design,a transparent sending mechanism was proposed,which could adjust the sending data packets format of MAC by means of bitmap.Additionally,an adaptive data receive mechanism for multiple channels in a round robin fashion was proposed,which cost only 25 % of traditional FPGA design in term of on chip memory resource.Utilizing the above interface model,only changing the corresponding value of several registers in FPGA can update the whole system and the adaptive data receive mechanism achieves a unified design that both AP and MT use the same FPGA code.All the registers were configured by protocol processor via peripneral component interconnett（PCI） bus and thus we need only generate the configure file for FPGA once,which saved great time cost by place and route procedure for FPGA due to generating different configure files.This design has very wide usage in future mobile communication systems.

关 键 词：超三代移动通信 时分双工 最优数据接口 现场可编程门列 先进电信运算架构 

分 类 号：TN92[电子电信—通信与信息系统]