DDS+PLL技术在C波段频率合成器中的应用  

Application of DDS+PLL Technology in C-band Frequency Synthesizer

作　　者：雷梁[1] 郑萍[1] 徐涛[1] 

机构地区：[1]西华大学电气信息学院,四川成都610039

出　　处：《现代电子技术》2008年第9期94-97,共4页Modern Electronics Technique

摘　　要：提出了一种具体的C波段小步进频率合成器的设计方案。该方案是基于锁相环频率合成（PLL）和直接数字频率合成（DDS）相结合的结构，利用DDS激励PLL产生所需信号。设计的信号频率范围为5．02-5．38GHz，频率步进为1kHz。重点阐述了系统的硬件实现，包括系统设计方案、主要电路模块设计以及系统测试结果等，并针对实际调试过程中常见的问题给出一些改进的方法。最后的测试结果表明了该频率合成器具有频谱纯、相噪低、杂散抑制能力强等特点，可以满足实际系统需要。A kind of design scheme about a concrete C- band fine resolution frequency synthesizer is proposed in this paper. This scheme based on the structure which integrated Phase Lock Loop（PLL） frequency synthesizing with Direct Digital Frequency Synthe- sizing （DDS） ,generating the needed signal with DDS impelling PLL. The designed frequency range is from 5.02-5.38 GHz,and the step range of frequency is 1 kHz. The focus of this paper is the hardware implementation including system design,circuit design of key module and test result of the whole system. Meanwhile, the paper gives a few improvements referring some familiar problems about the system while debugging. The last measured results show the performances of high purity spectrum, low phased noise, low spurious lev- el,and satisfy the requirements for the practical system.

关 键 词：直接数字频率合成器 锁相环 频率步进 相位噪声 杂散抑制 

分 类 号：TN74[电子电信—电路与系统]