嵌入式系统的动态功耗管理结构  

A DPM Architecture of Embedded Systems

作　　者：王力生[1] 康珊[1] 

机构地区：[1]同济大学计算机科学与工程系,上海200433

出　　处：《计算机技术与发展》2008年第8期188-191,共4页Computer Technology and Development

摘　　要：近几年来功耗问题成为在嵌入式系统领域中普遍关注的热点问题。其中动态功耗管理便是一种重要的减少系统范围的能量的方式。在近年的处理机设计技术中引入了支持基于动态电压与频率缩放的功耗管理的系统,主要提出一种基于这种技术的动态功耗管理的层次体系结构,它是基于"策略"的一种抽象定义。最后文章还用一个实例说明该结构不但能很好地完成复杂系统的功耗管理功能,而且具有较好的可扩展性,并且可以大幅度地降低系统功耗。Nowadays the energy consumption problem has become a main challenge in the embedded systems design. The DPM （dynamic power management） is an important solution of reducing energy consumption in the system level. In recent years,the dynamic voltage sealing techniques have been also used in the processors design. And aims at presenting a hiberarchy of DPM for the embedded systems which is based on those techniques. This architecture is an abstract definition on the basis of “policy”. Lastly an example is used to describe that the architecture not only can accomplish the complex system power management functions very well, but also has better sealability,and can significantly reduce the system power consumption.

关 键 词：嵌入式系统 动态功耗管理 层次体系结构 策略 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]