PLBMAP:高性能通用FPGA可编程逻辑块映射算法  

PLBMAP:A High Performance and Universal Programmable Logic Block Mapping Algorithm Based on FPGA

作　　者：蔡丹[1] 来金梅[1] 童家榕[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《微电子学与计算机》2008年第8期40-44,共5页Microelectronics & Computer

基　　金：国家自然科学基金项目(60776023);国家"八六三"计划项目(2005AA1Z12305-2)

摘　　要：研究了一种低复杂度、高利用率、高性能的通用FPGA逻辑块映射算法。基本思想包括为降低算法复杂度而提出的将组合电路与时序电路分开映射、对逻辑单元分层；引入匹配度系数以提高逻辑单元的利用率。从而在算法的性能和速度两方面均得到了较好的突破：平均性能比现存通用映射算法提高了12.59％，平均运行时间可以降低10^2～10^3倍。In this paper, we developed a low complexity, high utilization, high performance and universal programmable logic block mapping algorithm based on FPGA. The basic ideas include dealing with the combinational logic and sequential logic in the circuit severally, delaminate the circuit, and import the matching degree to improve the utilization of logic blocks. As a result, this algorithm has a breakthrough both in performance and run time. The results show that this algorithm performance equals to the special logic block mapping algorithms and even better than them, the average performance is 12.59% better than universal mapping algorithm, and the run time is 10^2--10^3 less than it.

关 键 词：现场可编程门阵列 可编程逻辑块映射 子图同构 匹配度 

分 类 号：TN47[电子电信—微电子学与固体电子学]