基于FPGA的新型高速FFT算法研究与实现  

Research and Implementation of a Novel Fast FFT Algorithm Based on FPGA

作　　者：顾艳丽[1] 周洪敏[1] 

机构地区：[1]南京邮电大学光电工程学院,南京210003

出　　处：《电子器件》2008年第4期1249-1251,共3页Chinese Journal of Electron Devices

摘　　要：提出一种新型基8/4FFT算法及其实现结构,设计出高速的处理模块。该设计可选择性地实现8k、4k及2k点FFT;通过乘法器的复用,有效降低硬件消耗;应用对称乒乓RAM结构提高了蝶型运算单元的连续运算能力。模块利用Ver-ilog语言进行描述,在Quartus5.0软件环境中完成输入、综合及布局布线。结果表明本文提出的算法结构具有优越的精度和速度,充分能够满足实际应用要求。A novel radix-8/4 FFT algorithm and architecture are introduced, fast processor is designed. The design can realize 8 k.4 k or 2 k point alternatively; obtain significant hardware reduction by multipliers multiplexing; increase the continuous computing capability of the butterfly core by using a symmetry pingpang RAM structure. The module is described with Verilog HDL,and performed with translated synthesized, routed in the Quartus5.0 software. The result shows that the algorithm architecture has achieved the expected purpose both on precision and speed, and can meet the demand of reality needs.

关 键 词：新型高速FFT 乒乓RAM 蝶型运算Verilog 

分 类 号：TN911.23[电子电信—通信与信息系统]