一种过零脉宽检测QPSK全数字解调器及其FPGA实现  

A Pulse-Duration-Detection QPSK Full Digital Demodulator and its FPGA Implementation

作　　者：韩露[1] 徐钊[1] 陈婕[1] 张晓光[1] 

机构地区：[1]中国矿业大学信息与电气工程学院,江苏徐州221008

出　　处：《通信技术》2008年第8期4-6,共3页Communications Technology

基　　金：国家自然科学基金项目资助(NO:50534050)

摘　　要：根据现代通信系统中调制解调技术全数字化的发展趋势和FPGA的广泛应用,文章提出并实现了一种采用过零脉宽检测方法、以FPGA为硬件载体的全数字QPSK解调器实现方案,并通过软件仿真和硬件测试验证了该方案的正确性和可行性。Since full digital modulation-demodulation in modern communication systems is becoming more popular and FPGAmore widely used, an implementation of full digital QPSK demodulator is proposed in this paper. The scheme is realized in FPGA and based on pulse-duration detection. Finally, its correctness and feasibility is verified through software simulation and hardware test .

关 键 词：QPSK FPGA 解调 过零脉宽检测 

分 类 号：TN763.3[电子电信—电路与系统]