四阶级联Sigma-Delta转换器设计  

Design of the fourth order cascaded sigma-delta modulator

作　　者：吴化林 王健[1] 

机构地区：[1]沈阳化工学院,110142

出　　处：《微计算机信息》2008年第23期305-306,共2页Control & Automation

摘　　要：在当今的DSP系统中,作为联系模拟世界与强大的数字领域的桥梁,ADC演了重要的角色。由于Sigma-Delta ADC很好地折衷了转换器的速度和精度,因此成为了用于通信系统中ADC的极佳选择。本文采用了2-1-1结构实现4阶调制器,设计了一个全差分增益提高Telescopic运算放大器,用于第一级积分器。采用了0.6μmN-Well CMOS工艺下加以模拟,电源电压为3v时,功耗为39Mw,调制器的信噪比达到87.3DB.ADCs fulfill an important role as the link between the analog world and the powerful digital processing environment in today＇s DSP systems. Among the wide variety of ADC architectures, Sigma-Delta ADC is an optimum candidate to meet the performance requirements of communication systems because it provides an efficient way of trading off speed for resolution. In this paper, the 4th-order modulator has been implemented with a 2-1-1 Cascaded Structure .A fully differential telescopic OTA with gain enhancement has been designed for the first integrator, the modulator is implemented with fully differential switched capacitor circuits. In 0.6μmN-Well CMOS process with a 3v power supply and dissipates about 39 Mw, The modulator achieves SNR of 87.3DB.

关 键 词：Σ-△调制器 级联结构 跨导运算放大器 非理想因素 

分 类 号：TP335.1[自动化与计算机技术—计算机系统结构]