数控高频振荡器的设计  

Design of Digitally Controlled High Frequency Oscillator

作　　者：李建成[1] 庄钊文[1] 谷晓忱[2] 关永峰[1] 陈亮[1] 

机构地区：[1]国防科技大学电子科学与工程学院,长沙410073 [2]国防科技大学计算机学院,长沙410073

出　　处：《微电子学》2008年第4期553-557,共5页Microelectronics

摘　　要：介绍了目前常用的数控延迟单元电路结构,详细分析了这些电路的优缺点。在此基础上,对其中一种电路结构进行了详细的理论分析,改进了电路结构,规范了电路设计的具体步骤,并通过大量的电路模拟,印证了理论分析的正确性。以此延迟单元为核心,在SMIC 0.13μm工艺下,设计实现了一款数控高频振荡器。该振荡器的频率范围高达700 MHz,最高稳定输出频率可达到1 GHz。由于采用全数字实现方式,其功耗最大值不到0.7 mW,版图面积只有26μm×36μm。该电路已成功应用于一个锁相环电路的设计中。Circuit structures of commonly used digitally controlled delay cell were described, and their advantages and disadvantages were analyzed in particular. A more detailed theoretic analysis was made on one of the circuits, and an improved structure was proposed based on the circuit. A high frequency digitally controlled oscillator was designed based on SMIC＇s 0. 13 μm technology. The oscillator had a maximum output frequency up to 1 GHz and a frequency range of 700 MHz. Realized with pure logic elements, the circuit, which was successfully used in a PLL, had a layout area of only 26 μm× 36 μm, and it consumed less than 0. 7 mW of power.

关 键 词：高频振荡器 数控振荡器 延迟单元 数控延迟单元 

分 类 号：TN752.2[电子电信—电路与系统]