基于Verilog-HDL的UART串行通讯模块设计及仿真  

Design and Simulation of UART Serial Communication Module Based on Verilog-HDL

作　　者：扈华[1] 白凤娥[1] 

机构地区：[1]太原理工大学计算机与软件学院,山西太原030024

出　　处：《计算机与现代化》2008年第8期11-15,共5页Computer and Modernization

基　　金：山西省留学人员科研资助项目(2004-26)

摘　　要：UART协议是数据通信及控制系统中广泛使用的一种全双工串行数据传输协议,在实际工业生产中有时并不使用UART的全部功能,只需将其核心功能集成即可。波特率发生器、接收器和发送器是UART的三个核心功能模块,利用Verilog-HDL语言对这三个功能模块进行描述并加以整合,通过Modelsim仿真,其结果完全符合UART协议的要求。The protocol of the UART, a full-duplex data transmission protocol, is widely used in data communication and control systems. In the industry, it dose not use all the functions of the UART but the core. There are three kernel functional modules in UART which consists of baud rate generator, receiver and transmitter. By using the Verilog-HDL to describe the three kernel functional modules of the UART, making them as a whole and simulating them with the Modelsim, the results of the simulation are completely consistent with the UART protocol.

关 键 词：UART 串行通讯 VERILOG-HDL MODELSIM 仿真 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]