信号串扰对高速模数转换器性能影响的分析  

Analysis on Signal Crosstalk Effects on Sampling Clock and Analog-to-Digital System

作　　者：孙磊[1] 安建平[1] 武岩波[1] 

机构地区：[1]北京理工大学信息科学技术学院

出　　处：《数据采集与处理》2008年第4期486-491,共6页Journal of Data Acquisition and Processing

摘　　要：基于实际电路的模数转换系统建立性能分析模型,分析电路信号串扰对转换时钟的干扰,并对转换时钟在信号串扰和噪声影响下的模数转换性能进行研究,推导出有信号串扰时的时钟抖动的模数转换解析表达式,证明转换结果含有和串扰信号频率相关的无穷多项高次谐波分量,并会导致模数转换器性能降低。仿真结果证明了相关分析的正确性,通过试验进一步说明了电路信号串扰对模数转换结果的影响。An analog-to-digital system performance analysis model is presented based on the real circuit system. The circuit signal crosstalk on sampling clock and its effect on analog-to- digital system performance are studied based on the model. An analytical expression for the A/ D conversion with such combined clock jitter error is developed. The expression shows that the combined clock error can generate infinite harmonic components on the converted digital signal. Computer simulations are in agreement with the developed expression. Also, a real experiment shows the evidence of the circuit noise influence on A/D performance and brings forth a comprehensive evaluation of analog-to-digital system design. This paper offers A/D designers a thumb rule to reduce the discrepancy between the actual circuit performance and the official figure imprinted on data sheet.

关 键 词：模数转换器 时钟抖动 信噪比 电路噪声 

分 类 号：TP335.1[自动化与计算机技术—计算机系统结构] TN241[自动化与计算机技术—计算机科学与技术]