FPGA可编程逻辑单元时序功能的设计实现  

The Design and Implementation of Sequential Circuits in FPGA Configurable Logic Block

作　　者：潘光华[1] 来金梅[1] 陈利光[1] 王元[1] 王键[1] 童家榕[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《电子学报》2008年第8期1480-1484,共5页Acta Electronica Sinica

基　　金：国家863高技术研究发展计划(No.2007AA01Z285);国家自然科学基金(No.60776023)

摘　　要：本文主要研究高性能FPGA可编程逻辑单元中分布式RAM和移位寄存器两种时序功能的设计实现方法.运用静态Latch实现分布式RAM的写入同步,以降低对时序控制电路的要求;为克服电荷共享问题,提出通过隔断存储单元之间通路的方法实现移位寄存器.以含两个四输入LUT(Look Up Table)的多功能可编程逻辑单元为例,详细说明电路的设计思路以及实现方法.研究表明,本文提出的方法可以简化对时序控制电路的设计要求,克服电荷共享问题,减少芯片面积.Abstract： This paper presented the design and implementation of two sequential circuits in FPGA configurable logic block,namely, distributed RAM and shift register. In order to decrease the rigorous demand of the liming controller, static latche is used to implement synchronous writing of distributed RAM.In order to eliminate the effect of charge sharing,the isolation is used to separate the passageway between ramcells. As an example of the CLB composed of two four inputs LUTs, the design and implementation method of the above sequential function is presented. It is concluded that the proposed method has its advantage in timing controller, charge sharing and die area.

关 键 词：FPGA可编程逻辑单元 分布式RAM 移位寄存器 

分 类 号：TN752[电子电信—电路与系统]