Parallel Algorithm Core: A Novel IPSec Algorithm Engine for Both Exploiting Parallelism and Improving Scalability  

作　　者：程东年 胡宇翔 刘彩霞 

机构地区：[1]National Digital Switching System Engineering & Technological Research Center

出　　处：《Journal of Computer Science & Technology》2008年第5期792-805,共14页计算机科学技术学报（英文版）

基　　金：supported by the National High Technology Development 863 Program of China (Grant No. 2005AA121210).

摘　　要：To deal with the challenges of both computation-complexity and algorithm-scalability posed to the design of an IPSec engine, we develop PAC （parallel algorithm core）, called PAC, employed in an IPSec engine, which can meet requirements of both exploiting parallelism existing in IPSec packets and offering scalability in both the scales and types of cryptographic algorithms. With three kinds of parallelism and two kinds of transparency defined, a novel hierarchy of the specifically-designed parallel structure for PAC is presented, followed by corresponding mechanisms. With a simulation, the scalability of PAC is examined. For the purpose of performance evaluation, a Quasi Birth-and-Death （QBD） process is then established to model a simplified version of the proposed PAC. Performance evaluation of PAC in terms of two representative measures, throughput and mean packet waiting time, is numerically investigated. A comparison study is done on a simulation basis. Conclusions are finally drawn for providing a helpful guideline for both the design and implementation of our proposal.To deal with the challenges of both computation-complexity and algorithm-scalability posed to the design of an IPSec engine, we develop PAC （parallel algorithm core）, called PAC, employed in an IPSec engine, which can meet requirements of both exploiting parallelism existing in IPSec packets and offering scalability in both the scales and types of cryptographic algorithms. With three kinds of parallelism and two kinds of transparency defined, a novel hierarchy of the specifically-designed parallel structure for PAC is presented, followed by corresponding mechanisms. With a simulation, the scalability of PAC is examined. For the purpose of performance evaluation, a Quasi Birth-and-Death （QBD） process is then established to model a simplified version of the proposed PAC. Performance evaluation of PAC in terms of two representative measures, throughput and mean packet waiting time, is numerically investigated. A comparison study is done on a simulation basis. Conclusions are finally drawn for providing a helpful guideline for both the design and implementation of our proposal.

关 键 词：computer network architecture IPSEC queuing theory parallel processing numerical analysis 

分 类 号：TP393.01[自动化与计算机技术—计算机应用技术]