A Novel 4/5 Prescaler with Automatic Power Down  

一种具有自适应节能的新型4/5高速双模预分频器(英文)

作　　者：曾隆月[1] 朱思奇[1] 阎跃鹏[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《Journal of Semiconductors》2008年第8期1449-1452,共4页半导体学报（英文版）

基　　金：国家高技术研究发展计划资助项目(批准号:SQ2007AA01Z238433)~~

摘　　要：An ＂automatic power down＂ method is introduced to design a 4/5 prescaler,with the characteristic of making one of its D-flip-flops power down when it operates in divide-by-4 mode. Implemented with the TSMC 0.25vm mixed-sig- nal CMOS process,the 4/5 MOS current mode logic prescaler is designed with this automatic power down technique. The simulation results show that the new 4/5 prescaler is immune to the ＂wake-up＂ issue and thereby retains the same maxi- mum operating frequency as the conventional prescaler. An integer-N divider with this proposed prescaler and with the di- vision ratio 66/67 is manufactured,and it is estimated to save more than 20% of the power compared with the conventional 4/5 prescaler.首次提出一种自适应节能方法用于设计4/5高速双模预分频器,它的特点是工作在除4模式时,其中一个D类触发器处于休眠状态.使用台积电混合信号0.25μm CMOS工艺,采用这一自适应节能的设计方法,设计了一个具有源极耦合结构的4/5高速双模预分频器.仿真结果证明,这一新型4/5高速双模预分频器不受休眠到工作转换状态的影响,最高工作频率保持不变.同时,流片结果表明,当这一新型高速预分频器用于实现66/67分频时,可节省高达20%以上的功耗.

关 键 词：MCML prescaler automatic power down frequency synthesizer 

分 类 号：TN773[电子电信—电路与系统]