高阶∑△ADC中的抽取滤波器的设计  

Design of a decimation filter used in ΣΔADC

作　　者：田涛[1] 叶英[2] 曾健平[2] 朱军[3] 

机构地区：[1]济宁学院信息技术系,山东曲阜273155 [2]湖南大学物理与微电子科学学院 微电子研究所,湖南长沙410082 [3]四川大学物理科学与技术学院,四川成都610065

出　　处：《电子技术应用》2008年第8期55-58,共4页Application of Electronic Technique

摘　　要：从电路实现和降低功耗的角度出发,优化并改进了梳状滤波器结构,同时设计了 FIR 补偿滤波器对其通带衰减进行补偿,通过合理的硬件电路安排来节省面积、提高速度,最终完成了高阶∑△ADC 中的抽取滤波器的设计。经过 Matlab 仿真,该滤波器阻带衰减为-65dB,通带纹波为±0.05dB,过渡带为0.454fs～0.583fs,经过 VerilogXL 和系统验证,该滤波器完全满足∑△ADC 的系统要求。The kind of decimation filter which is used in high-order ∑△ADC is given. Considering the hardware implement and minimize the power dissipation, techniques are applied to optimize the CIC filter structure. The FIR droop correction filter is also present to correct the pass band droop of CIC filter. The speed of this filter is improved and the area is minimized by using the correct circuit structure. Results from Matlab simulation show that the filter has stop band attenuation of-65dB, pass band rip-ple of±0.05dB and transition band of 0.454fs-0.583fs. According to the simulation of VerilogXL and system, the filter absolutely meets the requests of high-order ∑△ADC.

关 键 词：梳状滤波器 ADC 有限冲激响应 进位保留加法器 

分 类 号：TN92[电子电信—通信与信息系统] TN792[电子电信—信息与通信工程]