新型时延可控时钟网络驱动器及其应用  

Novel delay-controllable clock buffer and its application

作　　者：吕冬明[1] 张培勇[1] 严晓浪[1] 郑丹丹[1] 何仙娥[1] 

机构地区：[1]浙江大学超大规模集成电路研究所,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2008年第8期1350-1354,1414,共6页Journal of Zhejiang University：Engineering Science

基　　金：国家"863"高技术研究发展计划资助项目(2005AA1Z1271)

摘　　要：传统的时钟偏差调整方法在应用于超深亚微米工艺时，由于流程各阶段时序一致性的降低会产生失效问题．为此，提出了一种可重构的时延可控时钟网络驱动器（DCCB）的物理设计．该设计可以通过内部结构的重新配置来改变CMOS管的连接方式、连接级数以及各级的驱动能力，从而获得不同的传输延时．利用此特性，基于电路版图时序分析，通过重构DCCB单元进行时钟偏差调整，优化时钟周期．实验结果表明，与传统方法相比，此方法对时钟周期的缩减比例提高了10％～17％，而芯片面积及功耗保持不变．The decrease of the timing consistency in design flow at ultra deep submicron （UDSM） induces the invalidation of traditional clock skew scheduling approaches. Aiming at this problem, this work proposed a reconfigurable physical design of clock buffer, e.g. delay controllable clock buffer （DCCB）, which could alter its propagation delay according to the corresponding internal reconfiguration on the CMOS connection, the number of steps and the drive strength for each step. Based on the layout static timing analysis, the clock period was optimized by the clock skew scheduling utilizing the DCCB. Experimental results indicate that this approach improves the clock period by approximate 10%-7% higher than the traditional methodologies with the same area and power consumption.

关 键 词：时延可控时钟网络驱动器 时钟树 时钟偏差调整 

分 类 号：TN402[电子电信—微电子学与固体电子学]