Energy-efficient and security-optimized AES hardware design for ubiquitous computing  

作　　者：Chen Yicheng Zou Xuecheng Liu Zhenglin Han Yu Zheng Zhaoxia 

机构地区：[1]Dept. of Electronic Science and Technology, Huazhong Univ. of Science and Technology, Wuhan 430074, P. R. China

出　　处：《Journal of Systems Engineering and Electronics》2008年第4期652-658,共7页系统工程与电子技术（英文版）

基　　金：the "863" High Technology Research and Development Program of China (2006AA01Z226);the Scientific Research Foundation of Huazhong University of Science and Technology (2006Z011B);the Program for New Century Excellent Talents in University (NCET-07-0328).

摘　　要：Ubiquitous computing must incorporate a certain level of security. For the severely resource constrained applications, the energy-efficient and small size cryptography algorithm implementation is a critical problem. Hardware implementations of the advanced encryption standard （AES） for authentication and encryption are presented. An energy consumption variable is derived to evaluate low-power design strategies for battery-powered devices. It proves that compact AES architectures fail to optimize the AES hardware energy, whereas reducing invalid switching activities and implementing power-optimized sub-modules are the reasonable methods. Implementations of different substitution box （S-Boxes） structures are presented with 0.25μm 1.8 V CMOS （complementary metal oxide semiconductor） standard cell library. The comparisons and trade-offs among area, security, and power are explored. The experimental results show that Galois field composite S-Boxes have smaller size and highest security but consume considerably more power, whereas decoder-switch-encoder S-Boxes have the best power characteristics with disadvantages in terms of size and security. The combination of these two type S-Boxes instead of homogeneous S-Boxes in AES circuit will lead to optimal schemes. The technique of latch-dividing data path is analyzed, and the quantitative simulation results demonstrate that this approach diminishes the glitches effectively at a very low hardware cost.Ubiquitous computing must incorporate a certain level of security. For the severely resource constrained applications, the energy-efficient and small size cryptography algorithm implementation is a critical problem. Hardware implementations of the advanced encryption standard （AES） for authentication and encryption are presented. An energy consumption variable is derived to evaluate low-power design strategies for battery-powered devices. It proves that compact AES architectures fail to optimize the AES hardware energy, whereas reducing invalid switching activities and implementing power-optimized sub-modules are the reasonable methods. Implementations of different substitution box （S-Boxes） structures are presented with 0.25μm 1.8 V CMOS （complementary metal oxide semiconductor） standard cell library. The comparisons and trade-offs among area, security, and power are explored. The experimental results show that Galois field composite S-Boxes have smaller size and highest security but consume considerably more power, whereas decoder-switch-encoder S-Boxes have the best power characteristics with disadvantages in terms of size and security. The combination of these two type S-Boxes instead of homogeneous S-Boxes in AES circuit will lead to optimal schemes. The technique of latch-dividing data path is analyzed, and the quantitative simulation results demonstrate that this approach diminishes the glitches effectively at a very low hardware cost.

关 键 词：encryption and decryption power analysis model inhomogeneous S-Boxes ubiquitous computing advanced encryption standard. 

分 类 号：TB4[一般工业技术]