一种基于Muller流水线的异步流水线物理实现流程  

A Back-End Flow for Muller Asynchronous Pipeline Design

作　　者：王兵[1] 彭瑞华[1] 王琴[1] 

机构地区：[1]上海交通大学微电子学院,上海200240

出　　处：《上海交通大学学报》2008年第7期1173-1177,共5页Journal of Shanghai Jiaotong University

基　　金：总装备部预研项目(6130325)

摘　　要：为了克服异步电路实现工具不统一、实现复杂度较高的问题,提出了一种新的异步流水线实现流程.基于功能将实现流程分为同步时序约束和异步控制实现两个部分,对同步时序约束采用虚拟时钟,对异步控制实现采用真实延时控制,通过在实际的异步控制信号下的静态时序分析得到时序结果.实验和仿真结果一致表明,该流程可以完全利用成熟的电路自动化设计工具实现,极大地降低了异步流水线的实现难度.In order to overcome the shortcomin circuit generation tools and the high design g of asynchronous pipeline creation, such as lack of general difficulty, a novel asynchronous back end flow for asynchronous pipeline design was proposed. Based on function, it is divided into two parts named synchronous timing analysis and asynchronous control generation. Virtual clock is used for synchronous timing analysis and real control signals are used for asynchronous control generation. Actual timing of asynchronous pipeline is achieved from static timing analysis based on the control of asynchronous signals. The results of the flow used in simulation and testing signals show that it utilizes the EDA tools synchronous designs use and what designers need to do is just scripts generation, which reduces the design difficulty greatly.

关 键 词：异步流水线 同异步结合 时钟替换 设计流程 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构] TN402[自动化与计算机技术—计算机科学与技术]