An Improved High Fan-in Domino Circuit for High Performance Microprocessors  

高性能微处理器中一种改进的高扇入多米诺电路设计与实现(英文)

作　　者：冯超超[1] 陈迅[1] 衣晓飞[1] 张民选[1] 

机构地区：[1]国防科技大学计算机学院并行与分布处理国防重点实验室,长沙410073

出　　处：《Journal of Semiconductors》2008年第9期1740-1744,共5页半导体学报（英文版）

基　　金：the National High-Tech Research and Development Program of China(No.2005AA110020)~~

摘　　要：An improved high fan-in domino circuit is proposed. The nMOS pull-down network of the circuit is divided into several blocks to reduce the capacitance of the dynamic node and each block only needs a small keeper transistor to maintain the noise margin. Because we omit the footer transistor, the circuit has better performance than the standard domino circuit. A 64-input OR-gate implemented with the structure is simulated using HSPICE under typical conditions of 0.13μm CMOS technology. The average delay of the circuit is 63.9ps, the average power dissipation is 32.4μW, and the area is l15μm^2. Compared to compound domino logic, the proposed circuit can reduce delay and power dissipation by 55% and 38%, respectively.设计实现了一种改进的高扇入多米诺电路结构.该电路的nMOS下拉网络分为多个块,有效降低了动态节点的电容,同时每一块只需要一个小尺寸的保持管.由于省去了标准多米诺逻辑中的尾管,有效地提升了该电路的性能.在0.13μm工艺下对该结构实现的一个64位或门进行模拟,延迟为63.9ps,功耗为32.4μW,面积为115μm2.与组合多米诺逻辑相比,延迟和功耗分别降低了55%和38%.

关 键 词：high fan-in domino logic high performance keeper transistor 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]