指令优化设计与指令缓存结构相互关系的研究  

Mutual Effect of Instruction Layout Optimization and Instruction Memory Hierarchy

作　　者：王宇英[1] 周兴社[1] 

机构地区：[1]西北工业大学计算机学院,陕西西安710072

出　　处：《小型微型计算机系统》2008年第9期1694-1697,共4页Journal of Chinese Computer Systems

基　　金：国家高技术研究发展计划"八六三"项目(2006AA01Z162)资助

摘　　要：传统的指令优化方法通常不考虑调整指令高速缓存的硬件体系结构,只能得到局部优化结果.本文以实验的方法研究了指令优化设计和指令缓存配置之间的关系,通过实现程序指令优化并在不同指令缓存配置的平台上运行优化前后的程序,对比缓存缺失率,为进一步提高指令缓存性能提供了重要参考.实验结果表明指令缓存配置对指令优化的性能有极大的影响,在系统设计阶段同时考虑指令优化和指令缓存结构将能大幅度地改进指令缓存的性能.Traditional instruction layout optimization methods usually do not consider tuning the hardware architecture of the instruction cache in the optimizing process. Therefore, they trend to result in local-optimal solutions. This paper studies the mutual effect of the instruction layout optimization and the instruction memory hierarchy. We built a framework to perform the instruction layout optimizations, the original procedure and instruction layout optimized one are run on platforms with different cache hierarchy, and the cache miss rates are compared. Experimental results show that the instruction cache configuration greatly influences the benefit of instruction layout optimization, and the performance of the instruction cache could be potentially improved by jointly considering them together.

关 键 词：指令优化设计 指令缓存缺失率 缓存结构 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]