一种基于片同步技术的高速接口电路设计方法  

Design of High-Speed Interface Circuits With ChipSync Technology

作　　者：孙建涛[1] 马小兵[1] 陈兵[1] 华斌[1] 张平[1] 

机构地区：[1]中国科学院电子学研究所

出　　处：《测试技术学报》2008年第5期442-448,共7页Journal of Test and Measurement Technology

摘　　要：针对某合成孔径雷达系统的数据采集与形成模块，提出了一种基于现场可编程门阵列（FPGA）片同步（ChipSync）技术的高速数字接口电路设计方案。具体阐述了高速接口电路的结构框图、片同步技术的优点、高速接口电路时钟网络的分配和接口电路的详细设计方案。分析了时序余量以及数据同步，给出了系统调试方案以及实验结果。实验表明，当模／数变换器（ADc）的数据输出速率在50-600MHz范围之内时，ADC输出的数据能够可靠地锁存到FPGA内部。这种方案成功应用到某合成孔径雷达2400MHz采样率的数据采集与形成模块中。Focusing on the data acquisition and formation module of a certain synthetic aperture radar system, a design method for high-speed interface circuits with ChipSync technology based on Virtex-4 FPGA is presented. The system architecture of the high speed interface circuit, the merits of ChipSync technology, clock distribution and details of the design are expounded. Also, timing margin and data aligning are described. An entire debugging scheme of the system and the experimental results are intro-duced. The results demonstrate that the data from analog-to-digital converter can be received by the FI-FO within the FPGA device accurately when the rate of the data varies from 50 MHz to 600 MHz. The approach has been applied to the data acquisition and formation module of a certain synthetic aperture radar system whose sampling frequency is 2400 MHz.

关 键 词：合成孔径雷达 数据采集与形成 高速接口电路 现场可编程门阵列 片同步技术 

分 类 号：TN957[电子电信—信号与信息处理]