嵌入式五级流水线CPU核的设计与实现  

The Design- implementation of embedded five Stage Pipeline CPU Core

作　　者：赖兆磬[1] 潘明[1] 许勇[1] 张辉[1] 

机构地区：[1]桂林电子科技大学计算机与控制学院,广西桂林541004

出　　处：《微计算机信息》2008年第29期32-34,共3页Control & Automation

基　　金：广西壮族自治区科学技术厅资助项目"汽车运行状况智能监控与实时故障诊断系统"(桂科能063006-5G-3)

摘　　要：本文基于FPGA平台设计并实现了一种嵌入式16位RISCCPU核。以MIPSCPU指令集为参考,完成指令集设计;对指令处理过程进行抽象,把指令分成取指、译码、执行、访存、写回五级流水处理,根据处理过程所需要的元件构建五级数据通路;针对流水线处理产生的数据相关构建旁路通路;根据五级数据通路及旁路通路所需要的协调信号构建控制通路;把数据通路和控制通路融合成CPU核。采用VHDL实现CPU核;在CPU核上运行测试程序,并给出仿真结果;在FPGA平台上对CPU核进行验证。结果表明了所设计CPU核的有效性。An embedded 16-bit RISC CPU core was designed and implemented on FPGA. Refer to MIPS instruction set, the instruction set was finished; Analyzing the process of each instruction, the process was divided into five stages which is IF, ID, EXE, MEM, WB. Then the five stages data path was constructed according to work unit which is needed in the process; Aim at the data hazard which hap- pens in the pipeline, the forward path was constructed; the control path was constructed according to the data path; the CPU core was composed of data path and control path. The CPU core was implemented with VHDL; the test program was run at the CPU core, then the simulation was presented; the CPU core was verified at FPGA hardware terrace. The result shows that the CPU core is effective.

关 键 词：FPGA CPU核 数据通路 控制通路 

分 类 号：TP332.3[自动化与计算机技术—计算机系统结构]