基于FPGA的晶闸管过零触发调功电路设计  

A Zero-triggered Circuit of Thyristor Power Regulator Based on FPGA

作　　者：袁新娣[1] 

机构地区：[1]赣南师范学院物理与电子信息科学系,江西赣州341000

出　　处：《微计算机信息》2008年第29期311-312,221,共3页Control & Automation

基　　金：利用FP-LD产生波长连续可调超短脉冲的特性研究及应用;颁发部门:江西省自然科学基金委员会(0612004)

摘　　要：本文针对传统的用模拟电路方法设计晶闸管过零触发脉冲电路的缺点,采用FPGA为核心,设计了一个8级功率可调的晶闸管过零触发电路,该电路包括三部分:过零脉冲产生;控制信号产生;负载触发脉冲产生。三相同步方波信号输入该电路后,将产生6路脉冲个数可调的过零触发信号,从而实现对负载功率的调节。文章采用QuartsⅡ平台仿真,VHDL语言实现编程,电路简单实用,可靠性高。In order to solve the problems arising from the traditional Zero- triggered Circuit of Thyristor based on the principle of analog circuit, this paper has designed a 8-grade power regulating zero-triggered circuit of thyristor with FPGA as its kernel, which is composed of three parts： one is used to product zero-triggered impulses; the second is used to product control single ;the third is used to product load＇s zero-trigging impulses. When the circuit has been input a three-phase synchro-rectagular wave, it will produce 6 groups impulses ,and the number of impulses for each group is adjustable, which, be used as zero-trigging impulses of thyristor to regulate load power. This design adopts Quarts II as emulation base and is programmed in VHDL language. The design is simple but practical and reliable.

关 键 词：晶闸管 调功器 过零触发 EPGA 

分 类 号：TN273[电子电信—物理电子学]