9位50 MSPS流水线结构A/D转换器研究  

Study on 9-Bit 50 MSPS A/D Converter with Pipelined Structure

作　　者：洪岳炜[1] 王百鸣[2] 

机构地区：[1]深圳大学光电子学研究所,广东深圳518060 [2]深圳大学信息工程学院EDA技术中心,广东深圳518060

出　　处：《微电子学》2008年第5期622-624,629,共4页Microelectronics

基　　金：国家自然科学基金重大研究计划资助项目(90407001);深圳市科技计划资助项目(200512)

摘　　要：提出了一个采用三级流水线技术的9位50 MSPS A/D转换器,具体分析了其内部结构,给出了在OrCAD/PSpice 10.5下的仿真结果和动态测试结果;对设计流水线A/D转换器的关键问题进行了讨论,分析了引入流水线技术的优点和缺点。A 9-bit 50 MSPS A/D converter with three-stage pipelined structure was presented. The internal architecture of the circuit was analyzed in detail. Results from simulation with OrCAD/PSpice 10. 5 were described, and dynamic performance test results were analyzed and discussed. Key issues on designing the pipelined ADC were dealt with, and advantages and disadvantages of the proposed pipelined ADC were analyzed.

关 键 词：流水线结构 A/D转换器 模拟余量 

分 类 号：TN792[电子电信—电路与系统]