一种3V 13位40MHz低功耗采样/保持电路  

A 3-V 13-Bit 40 MHz Low Power Sample/Hold Circuit

作　　者：应建华[1] 王文平[1] 

机构地区：[1]华中科技大学电子科学与技术系,武汉430074

出　　处：《微电子学》2008年第5期679-683,共5页Microelectronics

摘　　要：设计了一种3V 13位40MHz低功耗采样保持电路。该电路采用带增益提高的全差分折叠式共源共栅运算放大器,满足高速高精度的要求;同时,采用带哑元补偿管的栅压自举开关,减小了采样开关带来的非线性失真。使用XFAB 0.35μm CMOS工艺库,对整体电路和分块电路进行了仿真和分析。A 3-V 13-bit 40 MHz low power CMOS sample/hold circuit was designed. In this circuit, a fully differential folded cascode operational transconductance amplifier with gain-booster circuit was used to improce speed and resolution performances, and bootstrapped switch with dummy transistors was employed to minimize nonlinearity caused by MOS switch. The circuit was simulated and analyzed based on XFAB＇s 0. 35μm CMOS process.

关 键 词：A/D转换器 采样/保持电路 栅压自举开关 增益提高运算放大器 

分 类 号：TN45[电子电信—微电子学与固体电子学]